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Automotive Versions of Flash-based, Non-volatile FPGA Family

Lattice recently introduced AEC-Q100 qualified versions of its LatticeXP2 Instant-On FPGA family.  These are devices built using a process that includes SRAM Programmable Logic + FLASH Storage on a single-die.  Lattice has raised the capabilities of automotive FPGAs by offering new system-on-chip (SoC) features such as full-feature DSP blocks, pre-engineered source I/O blocks and its exclusive FlexiFLASH™ architecture.

The FlexiFLASH architecture integrates the configuration Flash on the same silicon die as the SRAM FPGA logic.  The non-volatile FlexiFLASH architecture enables Instant-On startup speed, FlashBAK capabilities as well as the additional benefits of fault tolerance and redundancy.  FlashBAK enables the contents of the Embedded Block RAM to be written back to the FLASH memory so that during subsequent device initializations, the EBR memory is loaded with the new values.

Automotive system designs are using a growing number of FPGA devices to add additional capabilities and flexibility.  The LA-XP2 provides designers the broadest offering for performance and features of any AEC-Q100 qualified FPGA.  The instant-on capability allows the LA-XP2 FPGA to be used for applications that cannot wait for a typical FPGAs to startup such as Engine Control Units, FlexRay and CAN interfaces, processor bus decoders, Power-on-Reset and low power designs using duty cycling.

Instant-On, Redundancy and FlashBAK, these are a few of the advanced features offered in the LA-XP2 that are enabling advanced automotive systems.

Power Awareness for Your FPGA Designs

When I am designing with FPGAs, I like being aware of their power consumption.

When FPGA power consumption is within your system power budget...

• Your system operates correctly
• You are not surprised during system power up
• Your system still functions well when you push the system speed and temperature

However, when FPGA power is over your system power budget...

• Your system can have functional problems under certain operating environments (note that advanced technology- 90nm or newer- FPGAs would have the highest power consumption at high temperature.)
• Peak power consumption could occur during power-up configuration from the external "boot" device (Flash or PROM).
  

To avoid potentially disastrous system issues, you need to be able to predict or be aware of your FPGA power consumption.  Lattice provides a FPGA power calculator either as part of the ispLEVER development software or a power calculator as a standalone software for the FPGA designer to estimate device power consumption.

Lattice's power calculator has two main options to calculate your FPGA power consumption:

1. Estimation mode: In an early stage of your FPGA design, you can simply enter the estimated number of functional blocks (PFU, EBR, I/O, etc.), operating frequency and device operating temperature (junction temperature).  Based on this information, the power calculator will provide an estimated FPGA device power consumption.  If your estimated numbers are close, you should be within approximately 20% of your final power requirements. 
2. Calculation mode: Once you have completed your FPGA design, your exact FPGA design netlist is loaded to the power calculator.  With this exact functional block utilization data along with the frequency and temperature of device operation, you should be able to predict FPGA power consumption within 10%.

Gone are the days when you can simply read the power numbers from the data sheet and use those numbers to budget for system power supply.  However, today's FPGA software tools can reasonably estimate power numbers that will work in your system environment. 

Fighting Microprocessor Obsolescence with FPGAs

This webcast will be a look at microprocessor obsolescence and how it affects customer’s products and how FPGAs provide the best replacement solution. The presentation will include several designs where customers have worked with Lattice Semiconductor to cost effectively recover from an End Of Life as well as protect themselves against future Microprocessor Obsolescence.

Join me Wednesday, June 25th, 2008 11:00 AM (GMT -07:00) PDT for the webcast and ask me questions at the conclusion. To join, click here or cut and paste the following link: http://latticesemi.webapp.intevista.com/event/1jzf4qhxn1

Advance Features Enable Lowest-Power CPLD

Lattice just introduced the ispMACH 4000ZE family of CPLD devices in densities ranging from 32 to 256 macrocells.  These offer the lowest standby power of any of the zero-power CPLDs.  One of the main features for reducing the power consumption is Power Guard, which provide an easy way to lower the operating power of the CPLD by disconnecting the logic array from external input signal changes.  Any logic that changes state consumes power, removing the external stimulus activity from the logic array when it is not needed suspends internal logic activity that results in a power savings. 

There are 2 to 16 Power Guard blocks within the CPLDs depending on the density of the device.  The Power Guard control consists of logic between the I/O pin and the input buffer.  The gating logic known as the Block Input Enable (BIE) signal is controlled by an output from one of the internal macrocells in the logic array.  The Power Guard feature is enabled or disabled on a pin-by-pin basis.

Features such as Power Guard contained in this new family of zero-power CPLDs are enabling additional integration within portable and battery powered applications that require ultra low power consumption.

Microcontroller Obsolescence Solution

There are very few customers that enjoy receiving the statement: “Dear customer, the microcontroller in which you invested years of development time and money and planned to have in production for another 10 years is going End-Of-Life!” There have been several popular microcontrollers and microprocessors that have gone EOL over the last few years as semiconductor suppliers consolidate and prune their product portfolios.

Customers have the choice of performing a last-time purchase or re-designing the product. Last time purchases are problematic in the areas of up-front cash outlays and forecast quantities. As far as redesign, a simple board layout change to support a different part is easy, but software compatibility is the major hurdle when moving to a different microcontroller family. Most companies have a large investment in their target software; changing to a new architecture typically requires a complex and costly software port as well as verification.

Lattice to the Rescue
Lattice recently helped a customer in just this situation. The customer had a microcontroller in continuous production for more than 15 years. Not wanting to tie up capital in a last-time buy, the customer looked for other alternatives.

The customer required the replacement to be exactly the same fit and function as the original microcontroller. In addition, external and internal timing, processor functionality and even the same binary program had to run with no modifications. This compatibility included embedded software timing loops in the legacy processor code.

The final hardware solution is a small mezzanine board that contains an instant-on LatticeXP2 FPGA, an ADC device and clock generator. A PLCC connection allows direct interfacing with the manufacturer’s PCB and provides a pin-for-pin replacement for the original microcontroller. As the LatticeXP2 contains on-chip FLASH memory to configure the logic on startup, there is no need for an external boot memory which reduced the board device count and allowed for a smaller final solution.

The software solution used a third-party Intellectual Property (IP) core from Digital Core Design. DCD is a Lattice IP partner that offers a number of microcontroller and peripheral IP solutions. DCD modified an existing microcontroller core to match the exact execution and peripheral set found on the obsolete device.

The pin compatible solution allowed the customer design team to focus their efforts on validating the IP core instead of performing a full hardware and software design and validation. The solution enabled by Lattice and DCD ultimately saved the customer time and money by not having to perform a total system re-design.

Conclusion
Microcontroller and Microprocessor obsolescence will continue, but fortunately there are easy solutions to the problem using FPGAs coupled with microcontroller IP. The Instant-On LatticeXP2 FPGA provides a secure and small footprint solution that also meet customer’s very long life requirements. Microcontroller IP from partners like DCD allows a very quick and cost effective solution to replace existing microcontrollers while retaining exact software compatible with the original design.

Digital Power Management for Analog Supplies

Along with digital programmable logic devices-- FPGAs, CPLDs, and GALs, Lattice also provides mixed-signal programmable devices. These products were originally know as ispPAC, short for "Programmable Analog Circuits". Over the years, Lattice's programmable analog devices have grown into mixed-signal devices, combining digital and analog, on the same chip.

The way these Lattice programmable mixed-signal devices are configured is by using a free Lattice software tool called PAC-Designer. A code snippet for PAC-Designer is shown on the right.

Through simulation utilities and direct programming of evaluation boards, PAC-Designer provides multiple ways to verify designs before use. Just like with FPGA software, algorithmic modifications that would require changing of components or re-spinning circuit boards if done traditionally, can be accomplished in PAC-Designer simply by pointing, clicking, and downloading.

The latest programmable mixed-signal devices from Lattice are called Power Manager II, which are principally used for-- you guessed it-- programmable power management. Power Manager II devices can simplify the task of developing and optimizing power management algorithms because the sequencing behavior itself, as well as all supply ramp rates, voltage monitoring thresholds, and timing can be changed quickly and easily through software.

Power Manager II devices bring into a single package, a collection of features that might require several ICs and dozens of discrete passive components if they were implemented using more traditional means.

Shyam Chandra from Lattice is holding a webcast on using the Power Manager II devices: "Digital power management of analog supplies"

This webcast will show how a centralized programmable power management IC could be used to implement most of the Digital Power Management features, while using analog DC-DC converters and LDOs.