Frontier

PLD Perspective

Hello World!

I believe that's how all new computer-based experiences are supposed to start -- and blogging is definitely a new experience for me.

I guess that I should introduce myself and provide a little personal background information. I am currently the Vice President of Oregon Product Development for Lattice Semiconductor. I have been in the semiconductor industry for exactly 30 years now, having started with Harris Semiconductor in June 1976. My entire career has been dedicated to the design and development of Programmable Logic Devices (PLDs) so, by this measure, I am probably one of the world's experts in this field.

I have always been very passionate about the PLD industry and the impact that these devices can have on the world of electronic system design. I have watched as this industry has matured from simple PLDs (Bipolar PALs/CMOS GALs with little more than 100 programmable gates) to the current generation of system-level integration devices with millions of gates, embedded memory, multiple clock domains and high-speed Gbps I/Os.

In spite of what others may tell you, believe me when I say that 30 years ago absolutely no one envisioned the potential for PLDs/FPGAs to be doing the things that they routinely do today. No one ever believed that PLDs could compete with ASICs on either cost or performance... we may have talked about it and hoped for it, but we never really believed that it could happen. The PLD industry just wanted to carve out a small niche where we could peacefully co-exist with our ASIC brethren.

Today, even though the ASIC market is still much bigger than the FPGA market, it is the FPGA that is the hunter and the ASIC that is the hunted -- and I am more enthusiastic about the PLD market than I have ever been.

So, what fundamental changes have occurred that have enabled this dramatic shift in the balance of power? I would point to the following:

a) CMOS TECHNOLOGY - The early PLDs, developed in the mid-1970's, were based on bipolar technology. By the early 1980's, it was became obvious that bipolar technology could never achieve the low power and high integration levels offered by CMOS. Transitioning to CMOS technology was the first fundamental step in the FPGA revolution.

b) RE-PROGRAMMABLE MEMORY - CMOS technology was also capable of supporting re-programmable memory techologies such as EEPROM/EPROM and SRAM - both of which were critical to the success of early CMOS PLDs. Today, we take re-programmable logic for granted, but the original bipolar PLDs were all (ugh!) One Time Programmable (OTP).

c) POWER SUPPLY SCALING - The 5V supply standard endured for many years. The microprocessor industry drove the scaling of supply voltages in the early 1990's -- first to 3.3V and then rapidly toward today's 1V supplies. Power supply scaling has allowed CMOS technology to move aggressively to the deep sub-micron devices that, today, can fit an entire dual-port SRAM cell in the same area that we used to need just to place a contact!! Yes, contacts used to be ~1 sq. micron and today, DP-SRAM cells consume less than 0.5 sq. micron. So, while early FPGAs offered only modest (and often insufficient) functional density, power supply scaling has allowed today's FPGAs to provide functional densities that meet or exceed nearly any application requirement.

d) CMP & PLANARIZED METAL - What is the one thing that "gate arrays" cannot get enough of? Can you say "interconnect"? The early FPGAs were built using only 2-3 layers of metal and it was nearly impossible to provide sufficient programmable routing resources to achieve high levels of utilization. Today, CPM and Planarization technologies allow FPGAs to implement more than 10-layers of metal interconnect and this translates directly into the ability to build very compact and flexible switch-matrix elements that offer amazing levels of utilization and performance.

e) MASK COST - Finally, as the technology moves inexoriably toward 45nm and below, the cost of an ASIC mask set is fast approaching $1M and is becoming prohibitive for all but the highest volume applications. In response to this challenge, the ASIC business has attempted to morph itself into a "Structured ASIC" business which is just a feeble attempt to become more like a FPGA (i.e. offer late-in-process, low-cost customization on a standard "platform" base-product). I believe that it is "too little, too late" for this business model and the ASIC business will continue to search (unsuccesfully) for a way to compete with the growing strengths and capabilities of FPGAs.

These radical changes in the technological landscape were impossible to foresee thirty years ago... I was there and I have watched the industry evolve. One can debate the first two items, but the last three were not on anyone's radar screen. The growing dominance of FPGAs in today's market is a direct consequence of all of these changes and it has been an exhilarating ride for all who have been involved -- most notably for those at Altera, Xilinx and Lattice - the three major players in the CMOS PLD Revolution.

Fast-forward to the present...

While some may say that the PLD industry is maturing and, as a result, slowing its pace of development, I have a very different opinion. Today, after thirty years, I am more enthusiastic about the potential of the PLD industry for accelerated growth and impact on the world than I have ever been. I will be happy to discuss my reasons for this belief in future posts.

Please feel free to share your perspective on this, or other, PLD-related topics on this blog. I look forward to establishing a mutually beneficial dialog with anyone that shares my enthusiasm for all things programmable!

Welcome!

David Lee Rutledge, VP Product Development

Why FPGA will jumpstart shift toward ESL

Hello, I'm Mike Kendrick.

I am the guy who writes the requirements for the SW design tools .

Given the scope of the FPGA design flow, as you would expect, I don’t do this by myself. I also don’t do it in a vacuum. My main objective of writing this blog is to spark some conversation with designers on some of the current directions that FPGA based design could and should go.

Historically, FPGA design flow has been in the wake of the ASIC design flow. As they say, “Today’s ASIC designer issue is tomorrow’s FPGA designer’s issue”. That is not entirely true as many of these issues are addressed with the design of the FPGA chip itself. For example, a designer using an FPGA has a low skew clock tree available as a feature of the FPGA, but they have to build that as part of their ASIC development (and thus, there are tools in the ASIC flow which enable this).

But many design challenges faced by a designer targeting FPGA were first encountered by the ASIC designer. I would expect that basic trend to continue, and we will continue to look at the design issues in the ASIC world for our planning. I am extremely interested in designer’s thoughts on what issues they have or anticipate emerging.

I also see where the FPGA designer will face issues that were not faced by the ASIC designer. These relate to FPGA applications that for various reasons were not ASIC applications. ASICs are characterized by high fixed costs to get the first chip built, and design changes are costly. ASIC is not a technology that lends itself to experimentation, unless that experimentation can be accomplished solely through software running on the ASIC. FPGAs are now big enough where they can be used unlike an ASIC could realistically ever be used. For example – ESL.

ESL stands for Electronic System Level, and I think was originally coined by Gary Smith at Gartner/DataQuest. It’s a term that has been applied to many things and many products (by many marketing people). My personal definition of it is, “the thing which is the next abstraction after RTL”. It’s not taking a big risk to forecast that a design paradigm will eventually emerge that will be at a higher level of abstraction, thus allowing mere humans to design even more complex systems. This has been the inevitable march of engineering (remember schematic?).

The basic promise of ESL is that it would allow designers to describe the function of their system, and design automation tools would convert that to an implementation. Some tool flows were developed (e.g. CoWare, Cadence SPW, Synopsys CoCentric Studio) and targeted at the ASIC designer. However, given the economics of ASIC, all the experimentation with implementation had to be done in simulation. Other than being slow, this also created a need for simulation models which take time and resources to develop.

FPGAs can go after the ESL problem with quite a different paradigm. Different system implementations can quickly be evaluated in-system to analyze system throughput. Given their size, it’s now possible to see the system-level results of making system level changes such as: moving functionality between the SW and HW, changing the communication structure (e.g. shared bus vs. point-point). In my mind, FPGA is a much better technology for realizing the potential of ESL. A potential hurdle to progress is the size of the available pool of engineers which have the system level expertise to work with both HW and SW in their chip implementation.

Connections

Earlier this week I visited the Design Automation Conference (DAC) in San Francisco. This got me thinking, why do we as a technology industry collectively spend millions of dollars on trade shows? The answer is connections.  These events, despite all the corporate glitz, help folks interact with potential suppliers and/or customers (depending on your perspective) and understand who they are doing business with.  That is what this blog is intended to be, an opportunity for Lattice and its customers to interact on a more human level.

Who is Gordon Hands?

A quick background on myself. My involvement in programmable logic started in 1995 when I joined the programmable logic division of AMD. After a couple of years this division was separated out as Vantis that was then acquired by Lattice.  During the last 11 years I have had the opportunity to help define and launch our successful MACH 4/A and MACH 4000 CPLD products along with many of the products in our Look-up Table (LUT) based line up, including the LatticeECP/ECP2/XP and MachXO products.  Currently, I am Strategic Marketing Director here at Lattice and continue to be involved in the definition and launch of silicon products along with spending a significant part of my time shaping our increasingly important Intellectual Property (IP) business.

Almost Nothing Turns Out As Expected

Few things in life turn out quite as you expect! This applies to career, love, family and also PLDs. As we plan and introduce new PLDs we spend a lot a time thinking about the applications in which designers will use them. Some applications turn out to be realistic, some fall by the wayside and of course our customers discover many more. I hope that this blog will be good forum to discuss how designers are using programmable logic, what is working and what is not.

Onto improved connections ........

Why I Blog

Since I have been asked to start blogging, I've given it some thought.  In my busy schedule do I really want to take on another task that I have to schedule?  Well, after much deliberation, I came to these conclusions of why I should blog. 

I have been in the PLD industry for close to 20 years. That's even old in dog years! All this time I have been in Applications Engineering and I have talked to countless engineers.  So I should be able to pass on all that life experience to make it easy for someone who might be facing a similar situation that I've been through.  If I can save them a few hours to a few weeks worth of struggling to solve a technical problem, that alone would be worthwhile starting my blog. 

Managing a group of Applications Engineers and interfacing with many more Field Applications Engineers, I am constantly answering questions, learning and figuring out technical problems.  My collegues at the office will tell you that my office and phone queue is usually 2 to 3 deep.  If I am not talking to a person, I am probably answering my email.  I hope to make my blog another communication avenue, not only for the external engineers but also for my collegues, my direct reports and the field engineers that I interface with on a day-to-day basis.  This should, of course, not replace any critical communications, but rather enhance information transfer for common information that I am repeating several times.  So I welcome your inputs and comments on my blog to make this communication work for everyone's benefit. Someone once said that being an Applications Engineer is like being nibbled to death by a bunch of ducks.  I hope to reduce the nibbling with this blog.

It's a rare opportunity for an engineer to express our own opinion.  With my blog, I hope I can honestly express what I feel about some of the issues and implementations related to the PLD industry. 

The general topics I will be following are:
1: industry relevent discussion/opinion
2: PLD tricks of the trade
3: Lattice product specific discussion/answers
4: response to the comments/email.

Let the blogging begin, and I will tell you how my expectations match reality after a few months.

Bertrand Leigh, Lattice Applications Engineering

About this blog

Frontier is a collaborative blog written by senior Lattice engineers. Our initial blog authors are David Rutledge, vice president of product development (and inventor of the original GAL device); Bertrand Leigh, director of applications engineering; Mike Kendrick, manager of product planning; and Gordon Hands, director of strategic marketing. All of our authors are employees of Lattice Semiconductor.

We hope you will find Frontier interesting and informative. But more than that, we hope you will want to take advantage of this unique opportunity to start an open dialog with some of our key innovators. Your comments and questions are encouraged and will be an influential driver of blog content.

Blog entries represent our authors' personal views and insights. While FPGAs are expected to be a popular subject, all Lattice-related topics are open for discussion. That said, our authors will not be discussing corporate revenue or share price, future product roadmaps and ship dates, or any proprietary and confidential information. Well, you expected as much, right?