PLD Perspective

Hello World!

I believe that's how all new computer-based experiences are supposed to start -- and blogging is definitely a new experience for me.

I guess that I should introduce myself and provide a little personal background information. I am currently the Vice President of Oregon Product Development for Lattice Semiconductor. I have been in the semiconductor industry for exactly 30 years now, having started with Harris Semiconductor in June 1976. My entire career has been dedicated to the design and development of Programmable Logic Devices (PLDs) so, by this measure, I am probably one of the world's experts in this field.

I have always been very passionate about the PLD industry and the impact that these devices can have on the world of electronic system design. I have watched as this industry has matured from simple PLDs (Bipolar PALs/CMOS GALs with little more than 100 programmable gates) to the current generation of system-level integration devices with millions of gates, embedded memory, multiple clock domains and high-speed Gbps I/Os.

In spite of what others may tell you, believe me when I say that 30 years ago absolutely no one envisioned the potential for PLDs/FPGAs to be doing the things that they routinely do today. No one ever believed that PLDs could compete with ASICs on either cost or performance... we may have talked about it and hoped for it, but we never really believed that it could happen. The PLD industry just wanted to carve out a small niche where we could peacefully co-exist with our ASIC brethren.

Today, even though the ASIC market is still much bigger than the FPGA market, it is the FPGA that is the hunter and the ASIC that is the hunted -- and I am more enthusiastic about the PLD market than I have ever been.

So, what fundamental changes have occurred that have enabled this dramatic shift in the balance of power? I would point to the following:

a) CMOS TECHNOLOGY - The early PLDs, developed in the mid-1970's, were based on bipolar technology. By the early 1980's, it was became obvious that bipolar technology could never achieve the low power and high integration levels offered by CMOS. Transitioning to CMOS technology was the first fundamental step in the FPGA revolution.

b) RE-PROGRAMMABLE MEMORY - CMOS technology was also capable of supporting re-programmable memory techologies such as EEPROM/EPROM and SRAM - both of which were critical to the success of early CMOS PLDs. Today, we take re-programmable logic for granted, but the original bipolar PLDs were all (ugh!) One Time Programmable (OTP).

c) POWER SUPPLY SCALING - The 5V supply standard endured for many years. The microprocessor industry drove the scaling of supply voltages in the early 1990's -- first to 3.3V and then rapidly toward today's 1V supplies. Power supply scaling has allowed CMOS technology to move aggressively to the deep sub-micron devices that, today, can fit an entire dual-port SRAM cell in the same area that we used to need just to place a contact!! Yes, contacts used to be ~1 sq. micron and today, DP-SRAM cells consume less than 0.5 sq. micron. So, while early FPGAs offered only modest (and often insufficient) functional density, power supply scaling has allowed today's FPGAs to provide functional densities that meet or exceed nearly any application requirement.

d) CMP & PLANARIZED METAL - What is the one thing that "gate arrays" cannot get enough of? Can you say "interconnect"? The early FPGAs were built using only 2-3 layers of metal and it was nearly impossible to provide sufficient programmable routing resources to achieve high levels of utilization. Today, CPM and Planarization technologies allow FPGAs to implement more than 10-layers of metal interconnect and this translates directly into the ability to build very compact and flexible switch-matrix elements that offer amazing levels of utilization and performance.

e) MASK COST - Finally, as the technology moves inexoriably toward 45nm and below, the cost of an ASIC mask set is fast approaching $1M and is becoming prohibitive for all but the highest volume applications. In response to this challenge, the ASIC business has attempted to morph itself into a "Structured ASIC" business which is just a feeble attempt to become more like a FPGA (i.e. offer late-in-process, low-cost customization on a standard "platform" base-product). I believe that it is "too little, too late" for this business model and the ASIC business will continue to search (unsuccesfully) for a way to compete with the growing strengths and capabilities of FPGAs.

These radical changes in the technological landscape were impossible to foresee thirty years ago... I was there and I have watched the industry evolve. One can debate the first two items, but the last three were not on anyone's radar screen. The growing dominance of FPGAs in today's market is a direct consequence of all of these changes and it has been an exhilarating ride for all who have been involved -- most notably for those at Altera, Xilinx and Lattice - the three major players in the CMOS PLD Revolution.

Fast-forward to the present...

While some may say that the PLD industry is maturing and, as a result, slowing its pace of development, I have a very different opinion. Today, after thirty years, I am more enthusiastic about the potential of the PLD industry for accelerated growth and impact on the world than I have ever been. I will be happy to discuss my reasons for this belief in future posts.

Please feel free to share your perspective on this, or other, PLD-related topics on this blog. I look forward to establishing a mutually beneficial dialog with anyone that shares my enthusiasm for all things programmable!

Welcome!

David Lee Rutledge, VP Product Development

Comments

[Dick James]

You're currently shipping 90-nm parts (I think) fabbed by Fujitsu. Any idea when 65-nm product will appear?

[dlrutledge]

Fujitsu will provide Lattice with cost-competitive, leading-edge 65nm technology for our next-generation FPGAs. Lattice tends not to announce future products before they are ready. Be assured that we are working on our next-generation FPGAs and will give further details on 65nm when appropriate.

[Douglas Huey]

Hi, I am an investor hoping to invest in Lattice. I want to understand the industry. Would anyone at Lattice mind to explain how does FPGA work ? How does a FPGA get programmed and be able to be altered in the field ? How does Lattice plan to win in the market place ? Thank you for your help.

[Grace Hitt]

Nice blog David!