Slow Inputs Acceptable For FPGA?

This is a common question I get when you have system requirements to drive relatively slow input signals into fast FPGA inputs.  "How can I prevent the inputs from causing output oscillation?"

The theory behind this FPGA input or any fast CMOS device input behavior is simple.  As the input rise time gets slower, the signal stays in the input transition point a longer period of time.  This combined with any signal noise associated with the transition causes the input translator to detect false transitions which in turn get translated to the output.  The end result usually is output oscillation.

You can effectively use an input series resistor with the FPGA's internal input bus-hold latches to improve the slow input ramp time tolerance.  It's been demonstrated in our lab that the input ramp time improves from hundreds of nanoseconds to microseconds. More details can be found in the technote posted on Lattice web site.

Comments

[jg]

The correct way to manage slow edges, is to have Schmitt options on the pin
IP buffers.
Anything else is a kludge.

[Bertrand Leigh]

Agreed, if we're designing the input buffers from scratch. Since I am an Applications guy, what you can expect from me is the best "kludge" possible for the parts that don't have the input Schmitt trigger. Also keep in mind that there is a speed trade off for any additional feature you put on the buffers.

[Simon Jackson]

how about a debounce programmable divider?

[bertrand leigh]

Cleaning up the slow input rise/fall time is the same concept as debouncing an input switch. You can use the same techniques that work for debouncing a switch such as a debounce programmable driver you suggested here. Depending on how slow of a rise/fall time you are trying to clean up, a simple input series resistor with input bus-hold latch may be enough.