Low-cost FPGA with SERDES

It's an exciting day at Lattice as we introduce the LatticeECP2M that:

1. enhances the amount of Embedded Block Ram (EBR) and
2. adds SERDES capability to the popular LatticeECP2 family.

The LatticeECP2M addresses the growing requirement for high-speed serial I/O interfaces in low-cost FPGAs.  Until now if you needed SERDES in an FPGA, your selection of FPGAs would be limited to high-end (i.e. relatively expensive) FPGAs.  In an continuing effort to bring premium features to affordable FPGAs, Lattice has added 4 to 16 SERDES channels (up to 3.125Gbps per channel) to the LatticeECP2M, a chip that already has a high EBR to LUT ratio, DSP blocks and DDR2 memory interface support.

As part of the product introduction, we will be conducting a series of webcasts over next several weeks, highlighting the new device's capabilities such as digital video interfaces, detailed device architecture and SERDES features.