Soft processor within an FPGA

As our recent announcements of the LatticeECP2M and LatticeMico32 products show, a lot has been going on at Lattice.  The LatticeMico32 soft processor has been a significant project for the SW tools group.  Kevin Morris' FPGA Journal article has a good summary of this product.

This soft processor was developed to address two long term trends:
1)   As the cost/gate of FPGA continues to drop, and the size of a design which can fit in an FPGA grows, there will be an increasing economic incentive to include a processor within the FPGA.
2)    A soft processor combined with the programmable logic fabric is a practical testbed for HW/SW co-design.

A lot has been written about HW/SW co-design: moving functionality between SW and HW to maximize performance/cost ratio. However, it has been mostly up to the user to cobble together the various tools to see if they can get HW/SW co-design to work.  In my opinion, this has resulted in the slow adoption of solutions, as I noted in my previous blog.  FPGA vendors are in a unique position to accelerate solutions in this area, perhaps heralding a truly new era of system design.

From the ground up, the LatticeMico32 flow was built to synchronize the HW and SW development work.  A key benefit of implementing a processor and its mix of peripherals (we use the SoC industry term "Platform" for this) in a programmable logic fabric is that the HW/SW interface can be flexible.  Functions can be added or deleted, the communications architecture can be tuned etc.

However, this additional flexibility should be offered without burdening the HW and SW developer with additional housekeeping.  This is a primary goal of the LatticeMico32 System tools, and is the cornerstone of co-design support.

I'd be interested in your thoughts on using a soft processor within an FPGA.  What do you believe are the reasons for using a soft processor, and how do you think they will, or will not, be adopted within your industry?

Comments

[Ken Boyette]

Lattice seems to be on the right track with Mico32; free license, open-source Wishbone interface, GNU tools and flexible configuration options. I like what I see so far.

[Mr X.]

I left s similar comment here a few days ago, but since it hasn't shown up yet, i assume it was lost in cyberspace.

So here we go again:

Questions:
What do you believe are the reasons for using a soft processor, and how do you think they will, or will not, be adopted within your industry?

Answer:
1. software is easier to implement than hardware.
so this will save you some development time

2. software is easier to test than hardware.
at my work, we are trying to move test logic to CPUs, because we don't want to implement complex testbenches in hardware. what happens if there is an error in the testbench? do we need testbenches for the testbenches??

3. software is easier to modify
sometimes the costumer is not yet sure what it wants, sometimes the specification is unstable.

4. real-time modification
partial and self configuration exists in some more expensive FPGAs. but with a soft core, you can usually upgrade your firmware in a split second even on the cheapest FPGAs.

also, you don't need to run the complete flow over and over again every time you change a tiny detail in your design. just compile and upload. this is really a time-saver, according to my experiences. which brings us to the next point:

5. rapid prototyping anyone?
replaces a large chunk of complex logic with a CPU. sure, it wont run at full speed, but it will get your design up and running in much shorter time. which in turn means LOWER PROJECT RISK, and your manager will love you for that :)

6. freedom
its give you a higher degree of freedom. you can trade area for speed by moving functionallity between hardware and software.

7. its cool, its fun!

8. here is a large project, written by the pro.
can be used for benchmarking . in fact, this is how we decided to switch to lattice for our latest design :)
I have heard that LEON3 is very popular among EDA vendors, and given that this is a real-world design, this means better tools for all of us.

in addition, you can always learn thing by looking at this kind of stuff. not only I have learned about CPU design by looking into variuos soft cores, I also have learned a lot of vendor-specific optimization tircks!

9 Mico32 is GPL!
which means people will start contributing to it. so in a few months, someone will add an MMU and run Linux on it...

And here are couple of reason for NOT using soft cores:

1. its more expensive than, say, an ARM9. be it in Hertz, Watts or Dollars...

2. 2-3K LUTS is a lot in some designs (yes, I know that Mico8 is much smaller). And if you dont have external memory, you also have to fit the program memory in the FPGA...

3. more things to learn, more tools to buy. more bugs to hunt...

4. with some soft cores, you are locked to a specific vendor even if the rest of your design is truly portable.

[Mike Kendrick]

Mr. X:
Very good points. You clearly have given this some thought. As you point out, generally if you can implement function in SW rather than HW (i.e. you can take the performance hit), you have much more flexibility. Good example with the Field upgrades. Moving test logic to CPU - that technique could be very powerful, particularly since building an HDL testbench is hard enough, making it synthesizable is even tougher. A lot of testbench work is done in C or at least behavioral HDL, so migrating it down to the chip would be much easier if it was run on a CPU.

Small point - Mico32 is not licensed under GPL. GPL compels users who make modifications to put those modifications back into the public domain if they ship them in a product - even if those modifications are not done to the base code. This is not always in the best interest of the user as it could require them to distribute the source of valuable (but unrelated to Mico32) IP. The Lattice "open IP core" license agreement was specifically designed to avoid this. This license agreement allows you to both protect your IP and contribute to the Mico32 ecosystem.

[Phil]

cool & free IP processor :=)