Speedy FPGA

It was very clear to my 4 year old when I read to him about speedy boats and speedy cars how fast they go. But how fast do FPGAs go?

I should give him credit for giving me the inspiration to write this piece: to try and explain FPGA speed to everyone so we can all have a similar baseline understanding on how to estimate FPGA operating speed.

The following functional areas determine the overall operating speed of the FPGA:

1. I/O interface
2. Logic implementation
3. Clock tree and PLL
4. Other functional blocks

The I/O speed is generally measured by input setup/hold time and output clock-to-out time. This will give us the raw speed in terms of frequency (MHz) or data rate (Mbps) of the individual I/O interface.  If an application requires multiple I/O pins, the skew between the pins will affect the I/O operation speed as well.

Logic implementation speed is generally determined by the internal register-to-register operation speed. The register-to-register speed is determined by the logic block and routing delays between the registers. The FPGA static timing analysis tool will report the register to register speed in MHz or point to point delay.

Clock tree delay skew and PLL (sysCLOCK PLL) speed also are part of the determining factor for the logic speed.  Clock tree delay skew will directly impact the logic register-to-register speed.  Again, the FPGA static timing analysis tool will report this as part of the register-to-register speed of operation in MHz. PLLs will generally be able to support the fastest speed that the registers and logic can operate.

Other functional blocks like Embedded Block RAM (EBR) and Multiplier (sysDSP) will also have their associated operating frequencies.  These operating frequencies are all taken into account into the overall speed of operation for the FPGA. 

The question "how fast do FPGAs go?" can be answered in terms of frequency in MHz.  But this simple frequency of operation is made up of all the components discussed above.  The following are the LatticeECP2 FPGA specifications for each component of speed. These specifications tell us how fast LatticeECP2 FPGAs go.

• I/O - 840Mbps generic LVDS
• Logic - 250MHz to 500MHz
• Clock tree/PLL - 420MHz
• EBR - 350MHz
• DSP - 325MHz