« WYSIWYG Does Not Apply for Input Noise | Main | FPGAs: Replacing ASICs? »

Comments

j

image is not viewable

Leonardo Padial

I think this Glitch Free as drawing here don't work OK.
If the D input of register are at Vcc the output in Q is alltime "1". Then the CLK_IN don't pass to the CLK_OUT.
Regards.

bleigh

This circuit has been proven to work well in hardware. The idea is to clock the top register with a positive edge of CLK_IN and bottom register with a negative edge CLK_IN. If you start out with both register in reset (zero), then you will get a low-to-high transition on CLK_OUT on positive edge of CLK_IN and a high-to-low transition on CLK_OUT on the negative edge of CLK_IN. Then, after AND2 gate delay later, both registers will reset before the next clock cycle. There is a timing requirement that your CLK_IN frequency cannot be faster than the gate delays. Typically, only slow clock will have double clocking issue that you will need this type of circuit. Hope this helps you explain the operation of the circuit.

The comments to this entry are closed.