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Is it applicable to use XP2 FPGA to replace CPLD(for glue logic) in embeded system? Can you tell me the IO status at the stage of power on to power stable?


The posting definitely applies to the LatticeXP2 device family. If you are looking at CPLD replacement, you may also look into MachXO and the first generation LatticeXP device families.

The I/O state during power up remains high-Z until all supplies are at a minimum valid levels. Please also pay attention to how you bring up the VCC (1.2V core power), VCCAUX (3.3V auxiliary power) and VCCIO (8 banks of I/O supply). All three of these supplies must be at the minimum valid levels for the I/O pins to be valid.

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