High-quality FPGA implementation in Verilog

To build a high-quality FPGA implementation you need to be familiar with the target hardware and write models that not only capture your algorithm but are written in a style that reflects the constraints of the hardware.

Troy Scott from Lattice is holding a webcast on this very topic: "Optimizing Verilog Coding for More Efficient FPGA Synthesis"

This webcast is focused on how to target interesting building blocks of the Lattice FPGAs: the LUT/Register fabric and the I/O hardware, embedded block RAM, and finally embedded DSP blocks.

Along the way he’ll show interesting models from white papers and synthesis style guides and focus on the device elements that can be largely inferred from register-transfer level HDL.

Hopefully the webcast will raise your confidence to tackle your own Verilog design for Lattice FPGAs.