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Advance Features Enable Lowest-Power CPLD

Lattice just introduced the ispMACH 4000ZE family of CPLD devices in densities ranging from 32 to 256 macrocells.  These offer the lowest standby power of any of the zero-power CPLDs.  One of the main features for reducing the power consumption is Power Guard, which provide an easy way to lower the operating power of the CPLD by disconnecting the logic array from external input signal changes.  Any logic that changes state consumes power, removing the external stimulus activity from the logic array when it is not needed suspends internal logic activity that results in a power savings. 

There are 2 to 16 Power Guard blocks within the CPLDs depending on the density of the device.  The Power Guard control consists of logic between the I/O pin and the input buffer.  The gating logic known as the Block Input Enable (BIE) signal is controlled by an output from one of the internal macrocells in the logic array.  The Power Guard feature is enabled or disabled on a pin-by-pin basis.

Features such as Power Guard contained in this new family of zero-power CPLDs are enabling additional integration within portable and battery powered applications that require ultra low power consumption.

Microcontroller Obsolescence Solution

There are very few customers that enjoy receiving the statement: “Dear customer, the microcontroller in which you invested years of development time and money and planned to have in production for another 10 years is going End-Of-Life!” There have been several popular microcontrollers and microprocessors that have gone EOL over the last few years as semiconductor suppliers consolidate and prune their product portfolios.

Customers have the choice of performing a last-time purchase or re-designing the product. Last time purchases are problematic in the areas of up-front cash outlays and forecast quantities. As far as redesign, a simple board layout change to support a different part is easy, but software compatibility is the major hurdle when moving to a different microcontroller family. Most companies have a large investment in their target software; changing to a new architecture typically requires a complex and costly software port as well as verification.

Lattice to the Rescue
Lattice recently helped a customer in just this situation. The customer had a microcontroller in continuous production for more than 15 years. Not wanting to tie up capital in a last-time buy, the customer looked for other alternatives.

The customer required the replacement to be exactly the same fit and function as the original microcontroller. In addition, external and internal timing, processor functionality and even the same binary program had to run with no modifications. This compatibility included embedded software timing loops in the legacy processor code.

The final hardware solution is a small mezzanine board that contains an instant-on LatticeXP2 FPGA, an ADC device and clock generator. A PLCC connection allows direct interfacing with the manufacturer’s PCB and provides a pin-for-pin replacement for the original microcontroller. As the LatticeXP2 contains on-chip FLASH memory to configure the logic on startup, there is no need for an external boot memory which reduced the board device count and allowed for a smaller final solution.

The software solution used a third-party Intellectual Property (IP) core from Digital Core Design. DCD is a Lattice IP partner that offers a number of microcontroller and peripheral IP solutions. DCD modified an existing microcontroller core to match the exact execution and peripheral set found on the obsolete device.

The pin compatible solution allowed the customer design team to focus their efforts on validating the IP core instead of performing a full hardware and software design and validation. The solution enabled by Lattice and DCD ultimately saved the customer time and money by not having to perform a total system re-design.

Conclusion
Microcontroller and Microprocessor obsolescence will continue, but fortunately there are easy solutions to the problem using FPGAs coupled with microcontroller IP. The Instant-On LatticeXP2 FPGA provides a secure and small footprint solution that also meet customer’s very long life requirements. Microcontroller IP from partners like DCD allows a very quick and cost effective solution to replace existing microcontrollers while retaining exact software compatible with the original design.

Digital Power Management for Analog Supplies

Along with digital programmable logic devices-- FPGAs, CPLDs, and GALs, Lattice also provides mixed-signal programmable devices. These products were originally know as ispPAC, short for "Programmable Analog Circuits". Over the years, Lattice's programmable analog devices have grown into mixed-signal devices, combining digital and analog, on the same chip.

The way these Lattice programmable mixed-signal devices are configured is by using a free Lattice software tool called PAC-Designer. A code snippet for PAC-Designer is shown on the right.

Through simulation utilities and direct programming of evaluation boards, PAC-Designer provides multiple ways to verify designs before use. Just like with FPGA software, algorithmic modifications that would require changing of components or re-spinning circuit boards if done traditionally, can be accomplished in PAC-Designer simply by pointing, clicking, and downloading.

The latest programmable mixed-signal devices from Lattice are called Power Manager II, which are principally used for-- you guessed it-- programmable power management. Power Manager II devices can simplify the task of developing and optimizing power management algorithms because the sequencing behavior itself, as well as all supply ramp rates, voltage monitoring thresholds, and timing can be changed quickly and easily through software.

Power Manager II devices bring into a single package, a collection of features that might require several ICs and dozens of discrete passive components if they were implemented using more traditional means.

Shyam Chandra from Lattice is holding a webcast on using the Power Manager II devices: "Digital power management of analog supplies"

This webcast will show how a centralized programmable power management IC could be used to implement most of the Digital Power Management features, while using analog DC-DC converters and LDOs.

High-quality FPGA implementation in Verilog

To build a high-quality FPGA implementation you need to be familiar with the target hardware and write models that not only capture your algorithm but are written in a style that reflects the constraints of the hardware.

Troy Scott from Lattice is holding a webcast on this very topic: "Optimizing Verilog Coding for More Efficient FPGA Synthesis"

This webcast is focused on how to target interesting building blocks of the Lattice FPGAs: the LUT/Register fabric and the I/O hardware, embedded block RAM, and finally embedded DSP blocks.

Along the way he’ll show interesting models from white papers and synthesis style guides and focus on the device elements that can be largely inferred from register-transfer level HDL.

Hopefully the webcast will raise your confidence to tackle your own Verilog design for Lattice FPGAs.

Low-Cost Automotive Power Management Solutions

Designing power management control systems in automotive applications has become quite complex due to the continuous changes in technology. While 5-volt devices are preferred by automotive engineers for the robustness of the I/Os, every new generation of devices require a new, smaller operating voltage. On-board management of all the multiple voltage supplies becomes quite a challenge.

Devices that require their supply voltages to be applied in a very specific sequence to insure correct operation further complicate this challenge. All too often a “traditional” power management solution is applied to these “turbo-charged” power management requirements, resulting in circuit board designs that are inefficient, costly and usually compromised by tradeoffs.

Looking for powerful, cost effective solutions, several automotive customers requested Lattice provide the popular power manager devices in an automotive temperature range. Lattice responded, and in February 2008 announced the release of the automotive temperature LA-ispPAC-POWER1014/A power manager devices. The Lattice POWR-1014/A are the only fully-programmable power managers offered in automotive temperature.

The POWER1014/A incorporates both in-system programmable logic and in-system programmable analog circuits to perform the special functions that are optimized for power supply control, sequencing and monitoring. The POWR-1014A has 10 analog inputs for voltage monitoring, and can control up to 14 outputs. A built-in reset generator is available for control of external microprocessors.

By using a programmable, mixed signal power management device. Automotive designers can standardize on this “power management PLD,” using the device across all the automobile's ECUs, resulting in reduced cost as well as increased reliability.