One of the most common questions that programmable logic
designers face today is how to connect unique, disparate modules in their
system. That is to say, “Block A needs
to talk to block B and vice versa. What bus should I choose?” There are a plethora of choices that the
designer can choose from, but what most designers really need is a proven,
simple-to-connect bus interface without the overhead of many proprietary bus
interfaces. Enter WISHBONE.
In case you’ve not heard of WISHBONE, it’s a popular, open
source hardware interface that is promoted by the OpenCores project (https://www.opencores.org). Being open source offers several advantages
for programmable logic designs:
Open source designs: The OpenCores project is the web’s main
proponent of the WISHBONE architecture.
In addition to its role as WISHBONE advocacy, the OpenCores website offers
many grass-roots built RTL modules that are available for users in both Verilog
and VHDL, many of which are of course, WISHBONE ready. This means that a designer can attach their
own WISHBONE design to one or several of these OpenCores designs, saving
development time on both core functionality and bus connectivity.
Perhaps the most subtle advantage of WISHBONE is its flexibility. Unlike most bus system, WISHBONE can be
implemented as any one major bus types including hierarchical, point-to-point,
or many-to-many. In addition, a WISHBONE
bus can be multi-master or single master and can be 8, 16, 32, or 64 bits wide. The net effect of this flexibility is that
WISHBONE is appropriate for programmable logic designs of almost any complexity.
Proven: The WISHBONE interface is a well-defined
standard, has been around for more than six years and has been implemented in
hundreds, if not thousands of systems. If
you want a flexible, but low-risk bus architecture, WISHBONE fits the bill.
As stated on the Opencores website: “The WISHBONE standard is not copyrighted, and is in the public domain. It may
be freely copied and distributed by any means. Furthermore, it may be used for
the design and production of integrated circuit components without royalties or
other financial obligations.”
Lattice and WISHBONE:
Lattice believes in the WISHBONE credo and has several resources for Lattice users:
LatticeMico32: This is Lattice’s own 32-bit “soft”
microprocessor. It has a native WISHBONE
interface and is free with an open IP core licensing agreement. The power of the LatticeMico32 lies not only
in the flexibility of the core itself (it’s synthesizable), but also that it
can be connected to any WISHBONE peripherals including open source cores or
your own, custom logic.
Designs: Lattice offers several freely downloadable WISHBONE reference
designs as a starting point for user designs.
These reference designs come complete with documentation, RTL, and
testbenches. WISHBONE modules include an
I2C bus master, a SPI controller, and a LatticeMico8 WISHBONE adapter. Again, since they are WISHBONE, these
reference designs can be combined with OpenCores designs or a LatticeMico32.
System Examples: Our successful MachXO Mini Evaluation Board
comes with a native demo (“Mini SoC Demo”) that illustrates the WISHBONE bus in
a working system. This demo includes our 8 bit LatticeMico8 soft processor, a
UART, an I2C master, and a SPI memory controller, all connected on a WISHBONE
bus. A Lattice user can examine the
WISHBONE bus connectivity by downloading the RTL and documentation for this
demo at our MachXO
Mini Development Kit website. At this website, find the “Demo Applications”
button under “MachXO Mini Development Kit Resources” at the bottom of the
page. You can also view a video of the
demo or experiment with it yourself by purchasing the board from the MachXO
Mini Development Kit website.