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FPGAs and Your 'Right' to a Timing Constraint

In applications engineering we are often asked, “Why is my simple FPGA design not routing?” or “Why does my CPLD design have such a large timing score?” Sometimes we’ll also hear “PAR is taking forever, and then it fails!” In many cases, the solution is embarrassingly simple: “Create a timing constraint!”

Any fan of police shows can probably recite the rights that the police read to the suspect (known in America as “Miranda Rights”), which include “You have the right to an attorney. If you cannot afford an attorney, one will be appointed for you.” FPGA designers should be aware of similar advice: “You have the right to use a timing constraint. If you don’t provide one, a timing constraint will be provided for you.” With lawyers, sometimes you get what you pay for. So it is with FPGA Place-and-Route (PAR) software – in most situations it is better to provide your own reasonable constraint.

Users of large CPLDs and small FPGAs will sometimes cram lots of simple logic into the limited space available with no clocking constraint specification. The assumption is that because the clocking requirement is so slow (e.g. 32 kHz,) no timing constraint should be necessary. These users make the presumption that the PAR engine simply will route the clocking network, albeit with a very inefficient and slow structure. As counter-intuitive as this seems, nothing could be further from the truth. Why? Read on….

PAR algorithms require a timing constraint. Without a user-defined timing requirement, the mapping process generates its own timing estimate and passes this to the PAR process. Your simple design suddenly must meet a court-ordered 30 Mhz constraint! To compound the problem, as your FPGA or CPLD resources near their capacity (e.g. 85 to 90% and higher), there are fewer and fewer logic tricks and routing channels available to alleviate the timing pressure. In the end, you’re stuck with a design that doesn’t meet timing or doesn’t complete PAR, simply because you (unwittingly) directed the tool to use a clock definition that was more aggressive than it needed to be.

Constraints (‘Preferences’ in Lattice lingo) are contained in Lattice Preference Files (.lpf). These text files can be edited with any simple text editor. In addition, Lattice Design software (ispLEVER and Diamond) provides GUI editors to simplify preference specification.

Get out of jail free! Add a single timing constraint to your design.

Analog For Nothing and Bits For Free: ADC’s Using LVDS Buffers

My apologies to Dire Straits.  However, their hit song “Money for Nothing” illustrates a tendency in common observers:  An expert can makes something which is difficult appear to be very easy.  Whether it be a rock star playing the guitar or a major leaguer fielding a sharp-hit ground ball, a ‘pro’ gets it done with minimum effort and maximum results.

Likewise and at first blush it may appear that measuring analog voltages with a digital device such as a CPLD or FPGA is difficult, if not impossible.  But by leveraging LVDS input buffers (present in larger MachXO CPLDs or most Lattice FPGA families) in conjunction with Sigma-Delta modulation, that which was once considered ‘difficult’ is made easy.  Maximum results are obtained with minimum effort – 8 to 12 analog-to-digital conversion bits are achieved for virtually ‘for nothing.’

How does this help you, the designer?  Say you have a small, cost-sensitive design with a small controller and Lattice CPLD.  You could install a dedicated power-supply supervisor device (at extra cost) to monitor the uC core voltage. Or…you route the supply voltage through a simple and inexpensive RC network to an LVDS capable input and directly measure the analog voltage input to an accuracy within millivolts.

To that point, Lattice has released a new reference design on our website, RD1066 – “Simple Sigma-Delta ADC.”  It is a high capability, parameterized Sigma-Delta convertor capable of producing thousands of samples per second at up to 10 bits of effective resolution.  At about 50 LUTS, multiple copies can be used to monitor multiple inputs - Multiple power rails, battery voltages, sensors or feedback controllers – with plenty of logic to spare for your application.

Now that, is an analog for (almost) nothing and bits for (almost) free.