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Digital Power Management for Analog Supplies

Along with digital programmable logic devices-- FPGAs, CPLDs, and GALs, Lattice also provides mixed-signal programmable devices. These products were originally know as ispPAC, short for "Programmable Analog Circuits". Over the years, Lattice's programmable analog devices have grown into mixed-signal devices, combining digital and analog, on the same chip.

The way these Lattice programmable mixed-signal devices are configured is by using a free Lattice software tool called PAC-Designer. A code snippet for PAC-Designer is shown on the right.

Through simulation utilities and direct programming of evaluation boards, PAC-Designer provides multiple ways to verify designs before use. Just like with FPGA software, algorithmic modifications that would require changing of components or re-spinning circuit boards if done traditionally, can be accomplished in PAC-Designer simply by pointing, clicking, and downloading.

The latest programmable mixed-signal devices from Lattice are called Power Manager II, which are principally used for-- you guessed it-- programmable power management. Power Manager II devices can simplify the task of developing and optimizing power management algorithms because the sequencing behavior itself, as well as all supply ramp rates, voltage monitoring thresholds, and timing can be changed quickly and easily through software.

Power Manager II devices bring into a single package, a collection of features that might require several ICs and dozens of discrete passive components if they were implemented using more traditional means.

Shyam Chandra from Lattice is holding a webcast on using the Power Manager II devices: "Digital power management of analog supplies"

This webcast will show how a centralized programmable power management IC could be used to implement most of the Digital Power Management features, while using analog DC-DC converters and LDOs.

High-quality FPGA implementation in Verilog

To build a high-quality FPGA implementation you need to be familiar with the target hardware and write models that not only capture your algorithm but are written in a style that reflects the constraints of the hardware.

Troy Scott from Lattice is holding a webcast on this very topic: "Optimizing Verilog Coding for More Efficient FPGA Synthesis"

This webcast is focused on how to target interesting building blocks of the Lattice FPGAs: the LUT/Register fabric and the I/O hardware, embedded block RAM, and finally embedded DSP blocks.

Along the way he’ll show interesting models from white papers and synthesis style guides and focus on the device elements that can be largely inferred from register-transfer level HDL.

Hopefully the webcast will raise your confidence to tackle your own Verilog design for Lattice FPGAs.

It's all about the gearbox: for low-cost ADC to FPGA interfacing, that is

Although I am a marketer, I am an online marketer. This tends to make me somewhat skeptical towards marketing claims, since my day-to-day job is to get rid of claims that can been seen as subjective on websites.

However, it turns out that our low-cost 90nm FPGAs, namely the LatticeECP2/M and LatticeXP2 do have differentiated I/Os in our industry-- I/Os that make them particularly well suited to interface between high-speed serial ADCs and FPGAs, deserializing the serial data from the ADCs, and preparing it for pre-processing within the FPGA or further processing outside the FPGA.

In order to reliably meet all timing restrictions and compensate for delay variations within the FPGA across deserializer instantiations in most FPGAs, one has to use PLLs/ DLLs to reestablish phase relationship within the FPGA. It is not difficult to get the deserializer logic to operate reliably as long as the data rate is low. But in general it is very difficult achieve timing closures on 8 instantiations of deserializers for data rates of greater than about 500 Mega samples in low-cost FPGAs.

However, this is not the case for Lattice low-cost FPGAs.

The Lattice I/Os, which are called in marketing terms pre-engineered sysIO I/Os, are used to convert the DDR data from the ADC into single data rate or SDR data.  Lattice's low-cost FPGAs I/Os are different because they have a built-in gearing function.

As, shown in the block diagram "ADC to FPGA deserialization", the Bit clock is common to Flops 1,2,3,4, 5, 8 and 9 shown as the dark green blocks. The data in flops 1 and 3 are captured into 4 and 5 during the second rising edge of the bit clock. During 3rd rising edge of the bit clock, the data from flops 4 and 5 will be transferred to 8 and 9 and at the same time the new data from flops 1 and 3 are captured into 4 and 5. Now flops 9,8,5 and 4 hold 4 bits of data waiting for a FPGA clock edge to transfer the contents to flops B, A, 7 and 6. This process is called 1:2 gearing.

The frequency of FPGA clock is half that of the bit clock frequency. So for the data bit stream speed of 840 mega Bits per second, the FPGA operates at 420 divided by 2 or 210 MHz to capture the data a nibble at a time--a nibble once in approximately 5 nanoseconds. This timing constraint can be easily met across multiple instantiations in the low-cost 90nm FPGAs from Lattice. And key is that the user does not have to manually place and route these deserializers to meet timing.

Learn more by watching our latest webcast on the topic: "Interfacing High Sample Rate ADCs to FPGAs."

Gold Panning in Webcasts

I don't know about you, but when I attend a webcast, I just want to hear "the good stuff". You know, the gold nuggets. I don't want to sit there and waste my time saying "Yeah, Yeah, OK, OK, say something I don't know already."

Don't get me wrong, simple concepts can be important. But I want to know not just what "in theory" you can do, but what action you can take based on that concept. We are very busy creatures, and I want to be able to take action based on my 60 minute investment in attendance. When the webcast's over, I want to know that my time was well spent, and that it's caused a change in my (sometimes stubborn!) thinking.

Our next webcast is on Wednesday, March 28. The topic is "Tips for FPGA Timing Closure." The presenter will be Troy Scott, from our software marketing group.

Please attend or pass along an invitation to attend by registering at:
http://www.latticesemi.com/corporate/webcasts/tipsforfpgatimingclosure/index.cfm

Let me know how Troy does in his quest for solid gold!