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Who needs models?

Who Needs Models...

Models have always been important for electronic system design at all levels, whether at the component level (IC design), the board level or the system level. In this case, I am not referring to the attractive fashion models such as Kate Moss but, rather, the less evocative models that are important to verify the proper functionality of electronic circuits and systems.

My experience as an IC designer started with the need for only one fundamental model. I needed a SPICE model for each of my transistors in order to use a circuit simulator to verify the speed, power and functional characteristics of my design. I did not need a functional simulator (such as Verilog) because my first circuits were simple enough to "brain-sim" without the need for a computer-based logic simulator. I could do my entire job with a single circuit simulator.

Today, as a result of high levels of integration, we are truly integrating systems-on-a-chip. An IC designer must now perform sophisticated system-level modeling and simulation in order to verify the complex functionality of multi-million gate FPGAs. At the same time, the modeling and simulation requirements of FPGA customers have also grown substantially... and this is what I really want to talk about -- what are your needs as a end-user of FPGAs?

What models do you need...

Let's talk about the models and simulations that are now needed to support the application of FPGAs in today's electronic systems. In the final analysis, I want to know what you, the customer, believe to be the most important models that we can provide as a component supplier.

I will seed the conversation with a list of models that come to mind as important to our customers... please feel free to supplement this list with models that are missing or point out the models that are of particular importance to you.

TIMING MODELS

The timing model is used to determine performance-related characteristics such as FMAX and setup/hold timing violations. This model must comprehend pattern-dependent performance characteristics that comprehend the final P&R of the pattern with the FPGA. The model can be a very simple model or can extend to include the full PVT (process, voltage, temperature) variations of the FPGA.

FUNCTIONAL MODELS

Functional models (typically gate-level or behavioral) are important to allow board/system level functional simulations.

POWER MODELS

Lately, with deep sub-micron CMOS technology, the power levels of large FPGAs are very temperature dependent and power levels can increase dramatically at high temperature. Additionally, power is a strong function of application conditions such as supply voltage, pattern, clock frequency and output loading. Large FPGAs can easily exceed 5-10W power dissipation as a function of the foregoing variables. How important are Power Models to you? How do you verify that the Power Models accurately reflect the FPGA?

FAULT MODELS

Fault simulation is becoming more important as the functional integration levels grow. How does a system designer estimate the fault coverage for their test vectors? How does a system designer develop test patterns to fully test their board/system? Where does the FPGA fit into the overall Fault Simulation plan?

IBIS MODELS

The IBIS standard was developed by Intel many years ago in order to allow board-level signal integrity simulations to be performed without the need for a sophisticated SPICE simulation environment. Today, IBIS models are a common customer requirement. How important are IBIS models to you? How do you verify the accuracy of the IBIS models that vendors provide?

SPICE MODELS

In some cases, particularly Gbps I/Os, IBIS models are inadequate for board-level simulation needs. In these cases, the FPGA vendor will (begrudgingly) supply a more sophisticated I/O model in the form of an encrypted SPICE model. How important is this level of support for your designs?

BSDL FILES (IEEE-1149.1 & IEEE-1532)

This is another area of increasing need. Most modern systems include one or more 1149.1-compliant Boundary Scan chains. Many ATPG tools and ATE utilize the BSDL files to support the generation and application of board-level test patterns. Additionally, In-System Programmable parts (such as FPGAs) now use the IEEE-1532 extension to BSDL to support the generation and application of programming vectors to the programmable components on the board.

SOFT ERROR UPSET (SEU) MODELS

OK, now we arrive at a really esoteric model... Soft Error Upset (SEU) models. Today's large FPGAs have configuration bitstreams in excess of 50M bits -- now that's a lot of SRAM bits. The system-level MTBF due to SEU for FPGAs is becoming an important issue for certain customers and applications.

OTHER MODELS...

Now it is your turn to supplement and/or comment on the foregoing list of model requirements. Please share your perspective on the relative importance of the various models that you need. Please also share your views regarding which of the needs are being adequately addressed and which are being 'under-serviced' by your FPGA vendors. Feel free to rate and rank the various FPGA vendors in each of these areas. Your feedback will help shape Lattice priorities for model development and support in the future -- you can make a difference, so please share your views.

David Lee Rutledge, VP Product Development

PLD Perspective

Hello World!

I believe that's how all new computer-based experiences are supposed to start -- and blogging is definitely a new experience for me.

I guess that I should introduce myself and provide a little personal background information. I am currently the Vice President of Oregon Product Development for Lattice Semiconductor. I have been in the semiconductor industry for exactly 30 years now, having started with Harris Semiconductor in June 1976. My entire career has been dedicated to the design and development of Programmable Logic Devices (PLDs) so, by this measure, I am probably one of the world's experts in this field.

I have always been very passionate about the PLD industry and the impact that these devices can have on the world of electronic system design. I have watched as this industry has matured from simple PLDs (Bipolar PALs/CMOS GALs with little more than 100 programmable gates) to the current generation of system-level integration devices with millions of gates, embedded memory, multiple clock domains and high-speed Gbps I/Os.

In spite of what others may tell you, believe me when I say that 30 years ago absolutely no one envisioned the potential for PLDs/FPGAs to be doing the things that they routinely do today. No one ever believed that PLDs could compete with ASICs on either cost or performance... we may have talked about it and hoped for it, but we never really believed that it could happen. The PLD industry just wanted to carve out a small niche where we could peacefully co-exist with our ASIC brethren.

Today, even though the ASIC market is still much bigger than the FPGA market, it is the FPGA that is the hunter and the ASIC that is the hunted -- and I am more enthusiastic about the PLD market than I have ever been.

So, what fundamental changes have occurred that have enabled this dramatic shift in the balance of power? I would point to the following:

a) CMOS TECHNOLOGY - The early PLDs, developed in the mid-1970's, were based on bipolar technology. By the early 1980's, it was became obvious that bipolar technology could never achieve the low power and high integration levels offered by CMOS. Transitioning to CMOS technology was the first fundamental step in the FPGA revolution.

b) RE-PROGRAMMABLE MEMORY - CMOS technology was also capable of supporting re-programmable memory techologies such as EEPROM/EPROM and SRAM - both of which were critical to the success of early CMOS PLDs. Today, we take re-programmable logic for granted, but the original bipolar PLDs were all (ugh!) One Time Programmable (OTP).

c) POWER SUPPLY SCALING - The 5V supply standard endured for many years. The microprocessor industry drove the scaling of supply voltages in the early 1990's -- first to 3.3V and then rapidly toward today's 1V supplies. Power supply scaling has allowed CMOS technology to move aggressively to the deep sub-micron devices that, today, can fit an entire dual-port SRAM cell in the same area that we used to need just to place a contact!! Yes, contacts used to be ~1 sq. micron and today, DP-SRAM cells consume less than 0.5 sq. micron. So, while early FPGAs offered only modest (and often insufficient) functional density, power supply scaling has allowed today's FPGAs to provide functional densities that meet or exceed nearly any application requirement.

d) CMP & PLANARIZED METAL - What is the one thing that "gate arrays" cannot get enough of? Can you say "interconnect"? The early FPGAs were built using only 2-3 layers of metal and it was nearly impossible to provide sufficient programmable routing resources to achieve high levels of utilization. Today, CPM and Planarization technologies allow FPGAs to implement more than 10-layers of metal interconnect and this translates directly into the ability to build very compact and flexible switch-matrix elements that offer amazing levels of utilization and performance.

e) MASK COST - Finally, as the technology moves inexoriably toward 45nm and below, the cost of an ASIC mask set is fast approaching $1M and is becoming prohibitive for all but the highest volume applications. In response to this challenge, the ASIC business has attempted to morph itself into a "Structured ASIC" business which is just a feeble attempt to become more like a FPGA (i.e. offer late-in-process, low-cost customization on a standard "platform" base-product). I believe that it is "too little, too late" for this business model and the ASIC business will continue to search (unsuccesfully) for a way to compete with the growing strengths and capabilities of FPGAs.

These radical changes in the technological landscape were impossible to foresee thirty years ago... I was there and I have watched the industry evolve. One can debate the first two items, but the last three were not on anyone's radar screen. The growing dominance of FPGAs in today's market is a direct consequence of all of these changes and it has been an exhilarating ride for all who have been involved -- most notably for those at Altera, Xilinx and Lattice - the three major players in the CMOS PLD Revolution.

Fast-forward to the present...

While some may say that the PLD industry is maturing and, as a result, slowing its pace of development, I have a very different opinion. Today, after thirty years, I am more enthusiastic about the potential of the PLD industry for accelerated growth and impact on the world than I have ever been. I will be happy to discuss my reasons for this belief in future posts.

Please feel free to share your perspective on this, or other, PLD-related topics on this blog. I look forward to establishing a mutually beneficial dialog with anyone that shares my enthusiasm for all things programmable!

Welcome!

David Lee Rutledge, VP Product Development