With increasing frequency, automotive manufacturers regularly inquire about using FPGAs in high-reliability systems. In this continuation posting, I will highlight solutions that mitigate potential SRAM corruption issues.
Part one of this blog posting discussed the unique benefits of using AEC-Q100 qualified LatticeXP2 Non-Volatile FPGAs to eliminate issues that surround SRAM-based devices. These include: hard failure of the boot memory, memory retention issues, deliberate tampering, memory erasure, and electrical noise.
Soft Error Detection
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large memory systems in high-reliability applications. As device geometries continue to shrink, the probability of soft errors in SRAM has become significant for some systems. Designers are using a variety of approaches to minimize the effects of soft errors on system behavior. The phenomenon is applicable to all devices that include SRAM cells, including: Microprocessors, DSP processors, SRAM devices and FPGAs including Antifuse devices that include memory.
SRAM-based FPGAs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an FPGA increase, the probability that a soft error will alter the programmed logical behavior of the system increases. A number of varying approaches have been taken to address this issue, most of which involve Intellectual Property (IP) cores that the user instantiates into the logic of the design, using valuable resources and possibly affecting design performance. The LatticeXP2 devices have a hardware implemented soft error detector that does not affect performance or heat dissipation of the devices.
The SED hardware in the LatticeXP2 devices consists of an access point to the FPGA SRAM configuration memory, SED controller circuitry, and a 32-bit register to store the CRC for the current bitstream (see Figure). Enabling the SED capabilities does require the use of several I/O pins. Subtracted from the overall pin count are 4 dedicated input pins as well as 4 dedicated output pins. These pins are used to enable and start the SED checking as well as providing the status of the SED operation.
During SED operation, the control circuits read the serial data stream data from the FPGA’s SRAM configuration memory and calculates a CRC. The calculated CRC result is then compared with the expected CRC that is stored in the 32-bit register. If the two CRC values do not match, there is corruption of the configuration memory and an external signal is set to a high value to indicate the error. The user has several options for using the error signal: ignore the error, log the error using an external processor or reload the SRAM configuration from the original load device.
The SED checking inside the LatticeXP2 SED offers security against SRAM corruption that does not impact the performance or operation of the user logic. FPGA designs implemented with the four items listed in part 1 of this posting can be considered ultra-reliable for startup and initialization. Designs that incorporate the SED circuitry complete the protection for normal operation and enable complete ultra-reliable FPGA designs.