Advance Features Enable Lowest-Power CPLD

Lattice just introduced the ispMACH 4000ZE family of CPLD devices in densities ranging from 32 to 256 macrocells.  These offer the lowest standby power of any of the zero-power CPLDs.  One of the main features for reducing the power consumption is Power Guard, which provide an easy way to lower the operating power of the CPLD by disconnecting the logic array from external input signal changes.  Any logic that changes state consumes power, removing the external stimulus activity from the logic array when it is not needed suspends internal logic activity that results in a power savings. 

There are 2 to 16 Power Guard blocks within the CPLDs depending on the density of the device.  The Power Guard control consists of logic between the I/O pin and the input buffer.  The gating logic known as the Block Input Enable (BIE) signal is controlled by an output from one of the internal macrocells in the logic array.  The Power Guard feature is enabled or disabled on a pin-by-pin basis.

Features such as Power Guard contained in this new family of zero-power CPLDs are enabling additional integration within portable and battery powered applications that require ultra low power consumption.