My apologies to Dire Straits. However, their hit song “Money for Nothing” illustrates a tendency in common observers: An expert can makes something which is difficult appear to be very easy. Whether it be a rock star playing the guitar or a major leaguer fielding a sharp-hit ground ball, a ‘pro’ gets it done with minimum effort and maximum results.
Likewise and at first blush it may appear that measuring analog voltages with a digital device such as a CPLD or FPGA is difficult, if not impossible. But by leveraging LVDS input buffers (present in larger MachXO CPLDs or most Lattice FPGA families) in conjunction with Sigma-Delta modulation, that which was once considered ‘difficult’ is made easy. Maximum results are obtained with minimum effort – 8 to 12 analog-to-digital conversion bits are achieved for virtually ‘for nothing.’
How does this help you, the designer? Say you have a small, cost-sensitive design with a small controller and Lattice CPLD. You could install a dedicated power-supply supervisor device (at extra cost) to monitor the uC core voltage. Or…you route the supply voltage through a simple and inexpensive RC network to an LVDS capable input and directly measure the analog voltage input to an accuracy within millivolts.
To that point, Lattice has released a new reference design on our website, RD1066 – “Simple Sigma-Delta ADC.” It is a high capability, parameterized Sigma-Delta convertor capable of producing thousands of samples per second at up to 10 bits of effective resolution. At about 50 LUTS, multiple copies can be used to monitor multiple inputs - Multiple power rails, battery voltages, sensors or feedback controllers – with plenty of logic to spare for your application.
Now that, is an analog for (almost) nothing and bits for (almost) free.
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