Board design engineers are faced with a dilemma for each new microprocessor based system design that they encounter: how to integrate more processor power management function with the least amount of risk. How can we implement voltage monitoring, reset generation and watchdog timers while as few components as possible, while at the same time, keeping a shorter development cycle?
Rather than taking a traditional approach to assessing the tradeoffs, I’d suggest that we need to carefully consider the two most critical definitions: What does “integration” mean and what does “risk” mean?
In board development discussions, integration usually means reducing the number of components on your board by bringing as much function as possible into as few components as possible. Likewise, risk is commonly associated with the complexity of the board that you are bringing to market.
I propose that the most accurate definitions of risk and integration imply both a physical aspect and a process aspect. That is to say, risk can be quantified not only from the physical complexity of a board, but also with the complexity of the process that brings the board to market. In the same way, integration can mean not only a reduced BOM (bill of materials) but also a simplified development process.
Whether risk and integration complement each other or not depends on how they are combined. Higher levels of power management integration can bring more risk if the new solution is unproven. On the other hand, higher levels of integration can actually reduce risk if new parts actually simplify the processes that are required to bring the board to market. The right balance is achieved when we can find new power management solutions that not only increases integration, but also reduce the risk.
The mission of the ProcessorPM POWR605 is to do just this. That is, to reduce complexity and risk not only in terms of the physical board itself, but also in the process that brings it to market. The ProcessorPM reduces the physical complexity of a processor power solution by bringing voltage monitoring, processor reset and watchdog timer functionality all under one roof. Higher integration and a reduced BOM translate into lower risk.
The ProcessorPM comes with a tested and pre-programmed, factory configuration. The factory configuration integrates voltage monitoring for 5V, 3.3V, 2.5V and 1.8V supply monitoring with a CPU reset and watchdog timer interrupt output generation. Although the user can change the programming, there is no need to do so if the default functionality suits their needs. All they need to do is include ProcessorPM into their schematics and select the appropriate strap values to set watchdog delays and reset pulse stretching. This simplifies the development flow and reduces risk by eliminating the need to develop and test a new configuration.
Integration and risk will continue to be factors in the ever advancing pace of microprocessor based systems. The savvy engineer will continue to look for ways to optimize both for their system power management.
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