Our industry has come to a point where engineers are expecting simulation models for everything we do. Without a simulation model, we appear to be lost in even making some basic engineering judgement.
Take for example, SSO (Simultanuous Switching Output) noise. This is not a new concept. We had dealt with this type of noise a while ago with 20-pin to 24-pin PDIP packages. In these PDIP packages, assigning the Vcc and GND pins to the corner pins gave us the largest lead inductance in the package that in turn caused significant SSO noise if we are not careful.
The basic concept of SSO noise is governed by the equation V=L*(di/dt).
- V is the SSO noise voltage generated by the simultanuousely switching outputs
- L is the combined inductance of the bond wire, lead frame and PCB connectivity components of the Vcc or GND path
- di/dt is the instantanuous switch current of each of the switching pins
No doubt, the industry has moved from simple PDIP packages to more complex packaging technologies with many combinations of I/O pins and drive settings that can switch simultanuously. Don't get me wrong, I am your typical engineer who would love to have a simulation model, if an accurate one is available, without having to take out a second mortgage on my house to get it.
So, are we to stop designing systems with SSO conditions because we don't have access to a SSO simulator? There are a few practical things you can do to minimize the affect of the SSO noise. This is based on understanding the principle and paying attention to pin assignments when you design your FPGA.
1) Understanding that instantanuous switching current di/dt is one of the two contributing factors, paying attention not to use excessive drive current (ie. using the appropriate programmable drive at 4mA, 8mA, 12mA, 16mA and 20mA) and the appropriate slew rate setting can minimize the contribution.
2) You can also distribute your simultanuously switching outputs across multiple GND pins on a given package will effectively reduce the SSO noise as well. This, again, is effectively reducing the di/dt.
3) The other component is the L, the Vcc and GND inductance. You don't have much control of the device packaging component of the L. You have to trust that the FPGA chip and package designer has taken care of providing you the most optimum L for a given package. However, the PCB component of the L should be minimized through the proper Vcc and GND layout techniques.
To give you a practical sense about how much SSO noise contribution you get in practice, our typical lab measurements of 16 contiguous outputs switching at 16mA, fast slew rate to a lumped 5pF load per pin can generate SSO noise in the order of 650mV for a >200 ball fpBGA package. This is assuming you have also taken care of proper Vcc and GND PCB layout.
Rest assured that we are working towards creating better simulation models, including SSO. It would be useful to have a model when we have to reliably design a DDR2 memory interface running at 400Mbps data rate with 64 I/O pins switching. But when you are implementing a 16- or 32-bit data bus interface to a microcontroller that is running at 33MHz, careful pin assignment and drive setting will go a long way to avoid SSO noise, without simulation.