Although I am a marketer, I am an online marketer. This tends to make me somewhat skeptical towards marketing claims, since my day-to-day job is to get rid of claims that can been seen as subjective on websites.
However, it turns out that our low-cost 90nm FPGAs, namely the LatticeECP2/M and LatticeXP2 do have differentiated I/Os in our industry-- I/Os that make them particularly well suited to interface between high-speed serial ADCs and FPGAs, deserializing the serial data from the ADCs, and preparing it for pre-processing within the FPGA or further processing outside the FPGA.
In order to reliably meet all timing restrictions and compensate for delay variations within the FPGA across deserializer instantiations in most FPGAs, one has to use PLLs/ DLLs to reestablish phase relationship within the FPGA. It is not difficult to get the deserializer logic to operate reliably as long as the data rate is low. But in general it is very difficult achieve timing closures on 8 instantiations of deserializers for data rates of greater than about 500 Mega samples in low-cost FPGAs.
However, this is not the case for Lattice low-cost FPGAs.
The Lattice I/Os, which are called in marketing terms pre-engineered sysIO I/Os, are used to convert the DDR data from the ADC into single data rate or SDR data. Lattice's low-cost FPGAs I/Os are different because they have a built-in gearing function.

As, shown in the block diagram "ADC to FPGA deserialization", the Bit clock is common to Flops 1,2,3,4, 5, 8 and 9 shown as the dark green blocks. The data in flops 1 and 3 are captured into 4 and 5 during the second rising edge of the bit clock. During 3rd rising edge of the bit clock, the data from flops 4 and 5 will be transferred to 8 and 9 and at the same time the new data from flops 1 and 3 are captured into 4 and 5. Now flops 9,8,5 and 4 hold 4 bits of data waiting for a FPGA clock edge to transfer the contents to flops B, A, 7 and 6. This process is called 1:2 gearing.
The frequency of FPGA clock is half that of the bit clock frequency. So for the data bit stream speed of 840 mega Bits per second, the FPGA operates at 420 divided by 2 or 210 MHz to capture the data a nibble at a time--a nibble once in approximately 5 nanoseconds. This timing constraint can be easily met across multiple instantiations in the low-cost 90nm FPGAs from Lattice. And key is that the user does not have to manually place and route these deserializers to meet timing.
Learn more by watching our latest webcast on the topic: "Interfacing High Sample Rate ADCs to FPGAs."